Jason ed6f79c6d3 FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache ...

FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2
DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency).

Matched filter: Migrate input_buffer_i/q from register arrays to BRAM
(~33K FF savings). Overlap-save uses register cache captured during
ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy.
New ST_OVERLAP_COPY state writes cached tail samples back sequentially.

Both changes pass 18/18 FPGA regression. Golden data regenerated for
+2 FIR latency baseline.

2026-03-19 20:39:01 +02:00

..

constraints

Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments

2026-03-19 16:47:59 +02:00

formal

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

scripts

Add Build 17 production build script with full 15-point analysis checklist

2026-03-19 17:07:02 +02:00

tb

FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

2026-03-19 20:39:01 +02:00

.gitignore

CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

2026-03-19 11:31:46 +02:00

ad9484_interface_400m.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

cdc_modules.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

2026-03-19 11:31:46 +02:00

dac_interface_single.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

ddc_400m.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)

2026-03-19 10:31:16 +02:00

edge_detector.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

fft_engine.v

Split fft_engine FSM: async reset for control, sync reset for DSP/BRAM datapath (Build 11)

2026-03-17 21:40:09 +02:00

fft_twiddle_32.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

2026-03-19 20:39:01 +02:00

frequency_matched_filter.v

Convert async→sync reset on DSP/BRAM datapath registers for timing closure

2026-03-17 20:11:13 +02:00

latency_buffer.v

Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts

2026-03-18 01:28:42 +02:00

long_chirp_lut.mem

Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)

2026-03-19 10:31:16 +02:00

long_chirp_seg0_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg0_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

matched_filter_multi_segment.v

FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

2026-03-19 20:39:01 +02:00

matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

nco_400m_enhanced.v

Improve timing margins with targeted datapath register tuning

2026-03-17 23:51:04 +02:00

plfm_chirp_controller.v

Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)

2026-03-19 10:31:16 +02:00

radar_mode_controller.v

Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs

2026-03-17 12:47:22 +02:00

radar_receiver_final.v

Wire matched filter range profile to USB, replacing Doppler placeholder

2026-03-19 12:33:40 +02:00

radar_system_top_te0712_dev.v

Add TE0712/TE0701 split target with dedicated top, XDC, and build flow

2026-03-18 03:57:26 +02:00

radar_system_top_te0713_dev.v

Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments

2026-03-19 16:47:59 +02:00

radar_system_top.v

Fix CFAR blocking assignment (= to <=) in clocked block, add Build 15 analysis report

2026-03-19 13:22:15 +02:00

radar_transmitter.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

range_bin_decimator.v

Fix range_bin_decimator overflow guard priority bug: group completion now takes precedence over overflow guard in ST_PROCESS, ensuring all OUTPUT_BINS outputs are emitted when sufficient input samples exist. Split formal property 5 into 5a (upper bound) and 5b (exact count when start_bin=0), added Cover 4 for overflow guard path, reduced BMC depth to 50.

2026-03-17 15:41:06 +02:00

run_regression.sh

CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

2026-03-19 11:31:46 +02:00

short_chirp_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

short_chirp_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

usb_data_interface.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00