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e5d1b3cfc31e2661a86337117fa6df10c4af1408
PLFM_RADAR/9_Firmware/9_2_FPGA/tb
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Jason e5d1b3cfc3 Gap 4 USB Read Path: wire host-to-FPGA command path with toggle CDC, add read path tests 
- usb_data_interface.v: Add FT601 read FSM (RD_IDLE/OE_ASSERT/READING/
  DEASSERT/PROCESS) + cmd_data/valid/opcode/addr/value output ports
- radar_system_top.v: Connect cmd_* ports from usb_inst, add toggle CDC
  for cmd_valid (ft601_clk -> clk_100m), add command decode registers
  (mode/trigger/cfar_threshold/stream_control), wire host_mode and
  host_trigger to rx_inst
- radar_receiver_final.v: Add host_mode[1:0] and host_trigger input
  ports, replace hardcoded mode/trigger in radar_mode_controller instance
- tb_usb_data_interface.v: Connect cmd_* ports, add host data bus driver,
  add Test Groups 12 (single command), 13 (multiple commands), 14
  (read/write interleave). USB TB now has 55 checks.

Regression: 18/18 PASS
2026-03-19 23:16:26 +02:00
..
cosim
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
golden
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
ad9484_interface_400m_stub.v
Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)
2026-03-16 18:51:08 +02:00
cic_dc_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_impulse_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_sine_passband.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
ddc_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
fir_dc_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_impulse_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_sine_passband.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
gen_mf_golden_ref.py
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_summary.txt
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_pipeline_output.csv
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
nco_1mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_freq_switch.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_quadrature.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
radar_system_tb.v
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
2026-03-19 11:31:46 +02:00
tb_ad9484_xsim.v
Add new testbenches and fix USB clock forwarding test
2026-03-16 22:24:34 +02:00
tb_cdc_modules.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
tb_chirp_contract.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_chirp_controller.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_cic_decimator.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ddc_400m.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ddc_cosim.v
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
tb_ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
tb_doppler_cosim.v
Fix RTL Bug #3: S_IDLE->S_ACCUMULATE now writes first sample immediately
2026-03-16 19:08:16 +02:00
tb_edge_detector.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_fft_engine.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
tb_fir_lowpass.v
FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache
2026-03-19 20:39:01 +02:00
tb_freq_matched_filter.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_latency_buffer.v
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00
tb_matched_filter_processing_chain.v
Fix matched filter golden test paths (40/40 pass, was 37/40)
2026-03-19 12:20:37 +02:00
tb_mf_chain_synth.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
tb_mf_cosim.v
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
tb_multiseg_cosim.v
Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment
2026-03-16 19:15:23 +02:00
tb_nco_400m.v
Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)
2026-03-16 15:02:35 +02:00
tb_nco_xsim.v
Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization
2026-03-16 23:23:06 +02:00
tb_radar_mode_controller.v
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
tb_radar_receiver_final.v
Rewrite integration testbench with golden self-reference comparison + physics bounds checks
2026-03-17 20:56:28 +02:00
tb_range_bin_decimator.v
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
tb_usb_data_interface.v
Gap 4 USB Read Path: wire host-to-FPGA command path with toggle CDC, add read path tests
2026-03-19 23:16:26 +02:00
tb_xfft_32.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00