Jason d8a8532097 Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10) ...

CIC: async→sync reset on decimation control, valid pipeline, and comb
section. Added (* use_dsp = "yes" *) on comb[] to force DSP48E1
absorption of 28-bit subtracts (was 7-deep CARRY4, Build 9 critical
path at WNS +0.128ns). Targets ~10 additional DSP48E1s.

FIR: async→sync reset on delay_line block, enabling DSP48E1 AREG/BREG
absorption. Targets elimination of ~2,522 DPIR-1 methodology warnings.

13/13 regression suites pass. Integration golden: 2048/2048 exact match.

2026-03-17 20:56:42 +02:00

..

constraints

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

formal

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

scripts

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

tb

Rewrite integration testbench with golden self-reference comparison + physics bounds checks

2026-03-17 20:56:28 +02:00

ad9484_interface_400m.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

cdc_modules.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10)

2026-03-17 20:56:42 +02:00

dac_interface_single.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

ddc_400m.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

Convert async→sync reset on DSP/BRAM datapath registers for timing closure

2026-03-17 20:11:13 +02:00

edge_detector.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

fft_engine.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

fft_twiddle_32.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

Convert CIC comb + FIR delay_line to sync reset for DSP48 absorption (Build 10)

2026-03-17 20:56:42 +02:00

frequency_matched_filter.v

Convert async→sync reset on DSP/BRAM datapath registers for timing closure

2026-03-17 20:11:13 +02:00

latency_buffer_2159.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

long_chirp_seg0_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg0_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

matched_filter_multi_segment.v

Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment

2026-03-16 19:15:23 +02:00

matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

nco_400m_enhanced.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs

2026-03-17 12:47:22 +02:00

radar_receiver_final.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

radar_system_top.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

radar_transmitter.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

range_bin_decimator.v

Fix range_bin_decimator overflow guard priority bug: group completion now takes precedence over overflow guard in ST_PROCESS, ensuring all OUTPUT_BINS outputs are emitted when sufficient input samples exist. Split formal property 5 into 5a (upper bound) and 5b (exact count when start_bin=0), added Cover 4 for overflow guard path, reduced BMC depth to 50.

2026-03-17 15:41:06 +02:00

short_chirp_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

short_chirp_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

usb_data_interface.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00